library verilog;
use verilog.vl_types.all;
entity timing is
    port(
        adr             : in     vl_logic_vector(3 downto 0);
        read            : in     vl_logic;
        enable          : in     vl_logic;
        clk             : in     vl_logic;
        data_in         : in     vl_logic_vector(15 downto 0);
        BL              : out    vl_logic_vector(15 downto 0);
        BLB             : out    vl_logic_vector(15 downto 0);
        WL              : out    vl_logic_vector(15 downto 0);
        data_out        : out    vl_logic_vector(15 downto 0)
    );
end timing;
